TI launches next generation PCIExpress physical layer chip

Days ago, TI (TI) announced the launch of the third generation of discrete PCI Express physical layer (PHY) chip, the expansion of its PCI Express camp. The product has a high degree of flexibility, and can significantly reduce board space, designed to connect PC external card, communications, test equipment, servers and other embedded systems applications ASIC and low cost FPGA.

The new TI designed by PHY is in accordance with PCI Express 1.1 specification, and it is of great significance to realize interoperability with other PCI Express applications. The new device based on TI test chip. In addition, the solution also applies to TI currently listed on the PCI Express 1394a bridge technology with PCI Express.

TI PCI PHY Express has a 8 bit and a 16 bit interface, provides a high degree of design flexibility for circuit board designers. This interface is based on the Intel PIPE (PCI Express PHY) architecture specification version 1, the version has been slightly improved, to achieve a lower power consumption and easy integration of simplified interface.

TI PCI Express PHY sample will be listed in the second half of 2005, TI pricing on the device will make PCI Express ASIC and FPGA solutions in the market price advantage.

For the complete series of products including PCI Express framework for the development of product development strategy of TI, can achieve I/O chip to chip interconnection, interconnection adapter card, as well as the PCI Express and other I/O interconnection connections, such as PCI, 1394 (FireWire) and USB.