Toshiba display 32nm process NAND type flash test epitaxial wafer

Toshiba in Nano Tech 2009 (international nanotechnology integrated exhibition) (February ~ 20 ~ 18) on the display with 32nm technology NAND flash 300mm epitaxial wafer. The epitaxial film is imported into the 3bit/ unit technology 32Gbit products, will be in September 2009 to start mass production.

The component structure of the 32nm process is not much different from that of the 43nm (Toshiba). Like the original, floating gate structure. However, the number of electrons per floating gate in the 32nm process is reduced to about 200 (Toshiba). Thus, if the threshold voltage is divided into 8 units in order to achieve the 3bit/ unit, the write to the blank (Margin) becomes very small. In order to solve this problem, "in the circuit on a considerable amount of time" (Toshiba commentator). The company has been held in a few days ago, "International Solid-State Conference (ISSCC) 2009" on the release of the circuit technology.

Toshiba said the component technology is scheduled for the end of 2010 to 2011 of the 2Xnm production process, "is currently studying whether to extend the life of the floating gate structure, or the need for a nitride film trap (MONOS) new structure type" (Toshiba commentator). The industry believes that the floating gate structure due to interference between units and other issues, 3Xnm technology has been the limit, but Toshiba believes it may extend its life to 2Xnm. According to the production time speculated that the company will be concluded in the near future.

300mm epitaxial wafer integrated with 32nm process NAND flash memory

By the end of 2010 to 2011 production using 2Xnm technology products