Chip packaging size smaller Samsung developed 3D packaging technology

Samsung (Samsung Electronics), announced that it has developed a 3D chip packaging technology, its patented technology based on wafer level stack (WSP). Samsung's WSP technology using Si through the electrode (through silicon via) interconnection, to achieve a series of small mobile phone and other hybrid packaging.

The company's first 3D package consists of a 16Gb memory solution, stacked in the same unit 8 2Gb NAND chip. Samsung said that the technology is currently a multi chip package (MCP) size smaller version. Samsung's WSP prototype sample vertically stacked 8 NAND flash memory 2Gb 50 micron, height of 0.56 mm.

In the early days, Samsung will be in early 2007 to its WSP technology for the production of mobile applications and other consumer electronics based NAND memory card. Subsequently, it will use the packaging technology for high performance system package (SiP) solutions, as well as the server DRAM module, including high capacity DRAM stacked package.