Design and implementation of LED large screen control system based on FPGA

Compared to in liquid crystal display, projection display and other large screen display technology, LED display technology has its unique advantages: high brightness, wide viewing angle, rich colors and customizable screen shape. These features make LED display is widely used in industry, transportation, commercial advertising, information dissemination, sports competitions and other fields.

LED large screen control system is an integrated system which integrates computer control technology, video technology, photoelectron technology and communication technology. The current mainstream LED large screen control system to FPGA or FPGA combined with other chips as the main control chip. At present, LED large screen is moving toward the larger display area, showing a higher brightness, the color is more bright direction. All of these have brought new challenges to LED large screen control system.

In this paper, Altera's low cost Cyclone II series chip EP2CQ208C is designed based on LED large screen control system, the traditional SDRAM caching techniques, proposed SDRAM ping-pong cache technology optimization and elaborated the inverse gamma correction, color adjustment, gray level adjustment are realized in FPGA. The system finally achieved a maximum 1280 * 1024 resolution, a minimum of 240 Hz refresh rate of large LED screen display. At the same time through the PC software on the LED screen brightness, contrast, gray level and other parameters of the flexible adjustment, to get a more delicate display screen.

1 system architecture

In this paper, the design of the LED large screen control system structure is shown in Figure 1, the whole system is divided into two parts: the sending card and the receiving card. Based on Altera's EP2CQ208C as the main control chip, DVI data decoding uses TI's TFP201A (up to SXGA), the data cache uses the Samsung K4S643232C Gigabit Ethernet chip uses Realtek's RTL8212 (dual port Gigabit physical layer chip).

The data flow of this system is divided into control data and display data. Control data sent by the PC software on the FPGA card, send receive control data, determine the control card or send control data receiving card, if it is to control the receiving card, then send the data to the receiving card through the Gigabit network. TFP201A from the DVI interface for decoding display data by FPGA cache into SDRAM, and then read data in accordance with the display requirements for data block structure adjusted after packaged by RTL8212 is sent to the receiving card, receiving card receiving display data, and then drive LED display.

This paper mainly discusses the FPGA part of the system, including the following three points:

(1) optimization of SDRAM table tennis cache;

(2) anti gamma correction and gray level transformation based on RAM and PC software in FPGA;

(3) LED display brightness, contrast and other color adjustment in the realization of FPGA.

Optimization of 2 SDRAM ping-pong cache

The traditional SDRAM based ping-pong cache scheme [1, 2] has the disadvantages of complex data reading and writing operations or the limitation of data structure adjustment. Combined with the advantages of the existing scheme, this paper presents the SDRAM data cache scheme shown in figure 2.

The system is designed to send the card to support the maximum 1280 x 1024 resolution, the refresh rate of 60 Hz color data, at this time the pixel frequency:

That is to meet the requirements of system data throughput. Due to the same data storage two SDRAM, with the same format, so the SDRAM module can read and write at the same time to two SDRAM to write and read the display data, so SDRAM can share two address lines, so as to save dozens of FPGA IO port, which is a major advantage of this program. At the same time, each SDRAM is divided into two areas, in order to store the continuous two frame images, according to the specific requirements of the LED display, read out the data from the SDRAM, to meet the requirements of system flexibility.

3 inverse gamma correction and gray level adjustment

Under certain conditions, the image created in different environments, often appear the image looks too bright or too dark phenomenon, so the LED large screen display system needs to carry out flexible anti gamma adjustment. The current anti gamma correction based on FPGA internal ROM lookup table technology [3]. The formula (1) is the inverse gamma correction formula, the default input image gray level is, the output gray level is G, X is the input gray value, y is the output gray value, and the gamma correction coefficient. In order to realize the exponential operation in FPGA, it needs to consume a large number of logic units, which is not realistic for low cost requirements. In this paper, we propose an anti gamma correction technique based on the FPGA on-chip RAM, off chip EEPROM and PC software as shown in figure 3.

The specific implementation in FPGA is as follows: first of all, using the Altera core of the IP, 3 data width of 16 bit, the data depth of RAM of the two port instantiation as a look-up table. When the system starts, the initialization module reads out the 256 configuration data from the external EEPROM and initializes the RAM lookup table. After the initialization is completed, the gray level transform module separates the 24 bit RGB data into the 3 bit data as the RAM address, and the read data is converted into the gray value. When the need to modify the gamma value, through PC software to generate a new gamma correction table, and then sent through the serial port to send the card, send a card to send data to the receiving card, the control module will be under the gray transform data into RAM. If you need to save the calibration data, the initialization module reads data from the RAM into the EEPROM. The 3 RAM is stored in the same calibration data, so the initialization module can be initialized at the same time to the 3 RAM, read the configuration data from the RAM also need only one of the values in the. This method can be combined with PC software