Fujitsu launches statistical timing analysis system for ASIC and semiconductor foundry business

Fujitsu for ASIC and COT (customer owned tooling business: semiconductor foundry business) and other users, in October 2006 to provide for statistical analysis of the timing of the design environment. The use of statistical timing analysis of the design process, although the United States has been actively advocated IBM, but to provide a design environment for the actual ASIC/COT business users, Fujitsu is the first case.

The system provided for the use of existing timing analysis tools (STA:static timing analyzer) design process expansion. For the use of STA in the timing analysis of the path to become NG (basically critical path), the use of statistical timing analysis tools (SSTA:statistical static timing analyzer) for re analysis. The purpose of this paper is to use the SSTA to analyze the paths in the existing STA process in the presence of excess design allowance, which is called the worst case model.

Time reduction for timing optimization 30%

By using SSTA, timing analysis can be carried out considering the error of transistor production, thereby reducing the amount of excess. According to the different design and object reduction, but by reducing the excessive design margin, 90nm chip technology can improve the speed of 6%. In addition, because it does not need to have no practical significance to optimize the operation, about 30% of the time series can be reduced.

Fujitsu has just published a case in the microprocessor design using SSTA. Among them, SSTA is mainly used for yield prediction. The microprocessor provides the product according to the speed grade, and the ASIC method and the COT service are completely different. This time, will be used to modify the remaining surplus will be used SSTA. Users concerned about the quality and yield, "can guarantee the use of SSTA will not have an impact" (the company).

ASIC and COT will be the first to users of Fujitsu 90nm and 65nm production process (including internal users) and special dealers provide the design environment using SSTA. In addition, the design environment is also embedded in Fujitsu VLSI and Fujitsu Research Institute jointly developed by SSTA and the U.S. Anova Solutions statistical timing model making tool Anova Suite". Moreover, the Anova Suite is basically used by Fujitsu, users will use its output SSTA database.

Anova published in July 10th and Fujitsu jointly developed Anova Suite, etc.. Anova is a newly established enterprise in 2004, the founder of the current source model ECSM (Effective Current Source Model) and other developers, timing analysis stronger. According to Anova, is scheduled to be published before the end of the OPC relationship.