Software design of LED display screen

The program design of 1.LED display

For the transmission and control of data using the DMA of the S3C44BOX controller, the display program is simplified, the process as shown in figure. Transmission matrix code completion by DMA controller, only at the start of DMA data transmission will first address and the amount of data transmission, the address of the LED display dot matrix code values are assigned to the corresponding control word, DMA operation can be started. After the completion of all the same row of the lattice code transmission, the data will be stored in the second column of the data latch and output. In this way, the loop displays 16 frames of the same name and then completes a frame dot matrix display.

2 dot matrix ordering

Because LED display circuit module and the use of 16 bit parallel bus and DMA data transmission technology, the display of dot matrix emission in order to meet the following requirements:

A series of horizontal vertical cascade cascade two adjacent should be according to the principles in the dot matrix code sorting.

Fig. program flow chart

Due to the first column of data display driver module structure and DMA data latch decoding strobe circuit requirements, on the same display driver module on the two of the same name for Iraq should be according to the lattice column data latch strobe sequence for storage.

The 16 bit parallel bus to a data transmission, namely a DM write transfer two bytes of lattice code, low and high bytes are sent to the two adjacent longitudinal cascade module of the same name and name column data latch, namesake line and namesake vertical cascade module so the Zou dot matrix code should be stored.

In the 16 scan display mode, a large LED corpus is divided into 16 for each name, name for the dot matrix, sorted according to the second and the third and fourth in principle.

5 each stage in longitudinal lattice code sorted by 1, the second and the third in principle.

To sort the first name for a 128 * 64 dot matrix screen pixel data of the case (as shown), first name for storing order lattice codes should be as follows: A, b...... Z, A, B...... Z......

Figure 128 x 64 pixel dot matrix screen of the first row of the same name lattice code

Using parallel bus DMA data transmission technology, simplifies the LED display system software and hardware design, reduce the cost of the system, can achieve very good display quality. The system clock of 22.118 4MHz, 512 x 256 pixel monochrome display screen of the display frame rate of up to 250Hz, the average l20ns to send 1 bytes to use only CPU system instead of multi machine system control system on the LED display. However, in order to make the previous generation of the display driver board can still be used, lattice code needs to be sorted, the display can only be displayed on the page, so that multi page dynamic scrolling display requires large capacity memory. For 512 x 256 pixel monochrome dot matrix screen requires tens of megabytes of capacity, the use of the advanced controller of the 32 bit ARMTTDM core S3C44BOX and cheap large capacity SDRAM can make the problem is well resolved.

If used for the control of the DMA display driver board design, dot matrix code does not need to sort, a piece of hundreds of bytes of SRAM can meet the requirements of the system.

Called DMA (direct memory access), is a kind of high speed data transmission operation, allowing in external memory directly between the read and write data, neither by CPU, also do not need to pre CPU ten. The entire data transfer operation is carried out under the control of a DMA controller. In addition to the CPU at the beginning and the end of the data to do a little processing, in the transmission process CPU can do other work. Thus, in most of the time, the CPU and the input and output are in parallel operation. Therefore, the efficiency of the whole system is greatly improved. Because DMA allows access to peripherals as memory, exclusive formation of the bus, this system in hard real-time embedded development will cause the interruption delay is too long, it will in some occasions Gaocheng (such as heads of government organs, financial and military) is not allowed in the system.