TI 65 nanometer process through the verification of into production in early 06

Days ago, TI (TI) announced that its 65 nanometer process technology had been achieved, will be put into production, but this time from the relevant wireless devices samples first launched only 8 months time. TI said its 65 nanometer process technology in a more compact space for a variety of advanced applications to provide higher processing performance, and does not lead to increased power consumption. TI will face a wide range of target markets, including wireless communications, including the introduction of a large number of 65 nanometer technology products.

TI chief technology officer Hans Stork said: "TI's development objective is to promote the development of the technology itself has, first put into production in TI in a manufacturing plant, and then extended to multiple factories and foundries, to quickly provide customers to achieve high-volume manufacturing. In the industry, if we can advance the sample is very good, but the real competitive advantage is to see who can take the lead in the introduction of millions of high-quality products, so that suppliers can remain invincible."

TI first revealed in 2004 that its advanced 65 nanometer CMOS technology in detail, and announced the launch of wireless digital baseband processor samples in March 2005. Compared with the TI 90 nanometer process, the process technology makes the transistor density doubled, the function of the design area is reduced by half, while the transistor performance has reached a significant increase of up to 40%. In addition, TI technology greatly reduces the idle state of the transistor leakage current power consumption, but also integrates the on-chip system (SoC) configuration to support analog and digital functions of the hundreds of millions of transistors.

Through the realization of power management technology SmartReflex

At present, advanced multimedia and high-end digital consumer electronics requirements continue to increase, the low power semiconductor technology has become the focus of further development. In order to solve the challenges related to the management of the power supply, TI and performance of SmartReflex technology in its 65 nanometer silicon chip platform, adaptive and intelligent circuit design and the software together, in order to solve the technology node of smaller power and performance management problems.

SmartReflex technology without sacrificing overall system performance under the condition by closely monitoring circuit speed, dynamic voltage regulator to accurately meet the performance requirements. Therefore, in terms of all operating frequencies, we can properly use the lowest power, which extends the battery life, and reduce the heat generated by the device.

The other 65 nanotechnology can reduce the idle power consumption of the transistor, such as mobile phone standby power consumption etc.. These innovations include: reverse bias (back-biasing) of the SRAM storage area, which allows the voltage to drop to a very low retention trigger circuit, which does not require rewriting logic or memory contents. These SmartReflex innovative technology can reduce power consumption by 1000 times. Design flexibility and system optimization

TI has introduced a variety of technology options, after optimization, unique need to balance the various end products and applications, including extremely low power consumption to extend the implementation of various portable devices (such as 3G wireless handheld devices, digital cameras and audio player multimedia features such as growing equipment) battery life. End product support for DSP based products and TI for communications infrastructure products for high-performance ASIC libraries. TI 65 nm process for maximum performance support for server level microprocessors.

65 nanometer process comprises up to 11 layer integrated with low k dielectric copper interconnection layer, the dielectric material is organic silicate glass (OSG), the K (dielectric constant) value is 2.8-2.9. Other improvements include: the transistor channel has induced strain in the chip processing process (induced strain), can improve the electron and hole mobility; reduces the gate and source / drain nickel silicide gate resistor, and ultra shallow source / drain electrode is connected with surface technology.